FIG. 1 is a block diagram illustrating the basic configuration of a conventional image processing device. FIG. 2 is the timing chart of the image processing device shown in FIG. 1.
As shown in FIG. 1, said image processing device 10 comprises processing unit 13, which processes data in units of one scan line, memory unit 14 which can read and write in units of one scan line, and selector 15 which outputs the output data of processing unit 13 or the data read from memory unit 14 in accordance with a selection signal SL1.
Said processing unit 13 comprises an SIMD (single-instruction multiple-data) type image DSP (digital signal processor) which has multiple processor elements (PE) arranged in parallel with each other and executes the same processing in parallel manner in said multiple PE corresponding to the given instructions.
In image processing device 10 with the aforementioned configuration, the input image data ISIM of one scan line are synchronized by a clock to the same frequency as an external block and are supplied to processing unit 13 or memory unit 14.
The intermediate processing data T13 or T14 output from processing unit 13 or memory unit 14, respectively, are fed back to memory unit 14 or processing unit 13.
The image data S13 that have been processed in processing unit 13 or the image data S14 output from memory unit 14 are synchronized by a clock to the same frequency as an external block and output via selector 15.
However, in the aforementioned conventional image processing device, since clocks are used to transfer data of processing unit 13 and memory unit 14, which process image data in units of one scan line, and to input/output the image data to the outside, the processors can only be used at a low speed even if they can operate at high speed. As a result, the processibility cannot be fully exploited. Also, since it is necessary for processing unit 13 and memory unit 14 to input/output the fed back intermediate processing data T13 and T14 in addition to input/output images S11, S13, and S14, the number of input/output terminals is increased. This is a disadvantage.
One purpose of the present invention is to solve the aforementioned problems by providing an image processing device that can operate at high speed inside, even if the input/output with respect to the outside is performed at low speed and that can improve processibility to the maximum extent. Another purpose of the present invention is to provide an image processing device that can reduce the number of input/output terminals of processing unit 13 and memory unit 14 to a minimum.